Semiconductor integrated circuit device and process for manufacturing the same

ABSTRACT

There is provided a technique for forming an Ru film on the bottom of a deep hole with a considerable film thickness for the lower electrode of an information storage capacity element in order to improve the yield of manufacturing DRAMs. The Ru film is formed on the side wall and the bottom of a deep hole as material for preparing the lower electrode of an information storage capacity element to be produced there under the condition of a gasification flow rate ratio of the raw materials ((Ru(C 2 H 5 C 5 H 4 ) 2  /O 2 ) is not less than 10%. Then, the ratio of the film thickness of the Ru film on the bottom “b” of the hole to the largest film thickness “a” of the Ru film in the hole is not less than 50%.

TECHNICAL FIELD OF THE INVENTION

[0001] This invention relates to a semiconductor integrated circuitdevice and a process for manufacturing the same. More particularly, thepresent invention relates to a technique that can be effectively appliedto a structure comprising an insulating film having a hole (recess) anda metal film formed in the hole and containing Ru (ruthenium) asprincipal ingredient and also to a process for manufacturing such astructure.

BACKGROUND OF THE INVENTION

[0002] A DRAM comprises a MISFET for memory cell selection and aninformation storage capacity element connected in series to the MISFET.The information storage capacity element is typically formed bysequentially depositing silicon for forming a lower electrode, tantalumoxide for forming a capacity insulating film and silicon for forming anupper electrode.

[0003] The information storage capacity element is formed in a deep holethat is formed in insulating film in order to downsize the element and,at the same time, secure a certain degree of capacity.

SUMMARY OF THE INVENTION

[0004] However, when silicon is used for the lower electrode, a siliconoxide nitride film is formed along the interface of the silicon and theoxide tantalum deposited thereon in the heat treatment process conducted(at 800° C. for 3 minutes in an oxidizing atmosphere) for the purpose ofcrystallizing and improving the film quality of the tantalum oxide.Therefore, while the tantalum oxide and the silicon oxide nitride filmoperate as dielectric to suppress any possible leak currents, it isdifficult to make them show a high dielectric constant.

[0005] Additionally, as device is down-sized, the hole for forming theinformation storage capacity element also needs to be down-sized andeventually the undulations of crystallized silicon on the wall of thehole come to contact each other so as to eliminate any room for formingupper film layers such as the tantalum oxide film.

[0006] The inventors of the present invention have been engaged inresearch and development for materials that can be used for the lowerelectrode of an information storage capacity element. They are currentlylooking into the feasibility of using ruthenium (Ru) for the lowerelectrode in order to dissolve the above identified problems.

[0007] Ru does not form a low dielectric constant film such as oxidenitride film and can be used to form a thin film because it is metal.

[0008] However, in an experiment using an Ru film for the lowerelectrode, there appeared a phenomenon where the film thickness waslarge in an upper part of the side wall of the hole and was small on thebottom of the hole as shown in FIG. 25A. When such an Ru film issubjected to heat-treatment to improve the density thereof, the thin Rufilm on the bottom of the hole can agglomerate to produce islands of Ru(FIG. 25B). Then, the Ru film is discontinued and can no longer operateas lower electrode.

[0009] On the other hand, when the Ru film on the bottom of the hole ismade to show a large film thickness in order to secure the continuitythereof, the Ru film in the upper part of the side wall of the hole isincreased accordingly until it contact itself to eliminate any room forforming upper film layers including a tantalum oxide film (FIG. 26).

[0010] Thus, it is an object of the present invention to provide atechnique with which an Ru film can be formed effectively andefficiently in a hole for the lower electrode of an information storagecapacity element.

[0011] Another object of the invention is to provide a technique withwhich a desired Ru film can be formed to improve the performance of aninformation storage capacity element.

[0012] These and other objects and the novel features of the presentinvention will become apparent from the following description made byreferring to the accompanying drawings.

[0013] In an aspect of the invention, there is provided a process formanufacturing a semiconductor integrated circuit device comprising:

[0014] (a) a step of forming a MISFET for memory cell selection on themain surface of a semiconductor substrate;

[0015] (b) a step of forming a plug electrically connected to thesource/drain region of said MISFET for memory cell selection;

[0016] (c) a step of forming a silicon oxide film on said plug;

[0017] (d) a step of forming a hole getting to the surface of said plugin said silicon oxide film;

[0018] (e) a step of forming an Ru film on the side wall and the bottomof said hole by causing an organic compound of Ru and an oxidizingagent, the gasification flow rate of the organic compound of Ru beingnot less than 5% of the flow rate of the oxidizing agent;

[0019] (f) a step of forming a capacity insulating film on said Ru film;and

[0020] (g) a step of forming an upper electrode on said capacityinsulating film.

[0021] Preferably, the reaction of said organic compound of Ru and saidoxidizing agent is conducted at temperature not higher than 300° C.

[0022] In another aspect of the invention, there is provided asemiconductor integrated circuit device comprising:

[0023] (a) a MISFET for memory cell selection formed on the main surfaceof a semiconductor substrate;

[0024] (b) a plug electrically connected to the source/drain region ofsaid MISFET for memory cell selection;

[0025] (c) a silicon oxide film formed on said plug;

[0026] (d) a hole formed in said silicon oxide film and extending to thesurface of said plug; said hole having a depth not less than five timesof the short diameter thereof;

[0027] (e) a information storage capacity element comprises an Ru filmformed in said hole, a capacity insulating film formed in on the Ru filmand an upper electrode formed on the capacity insulating film;

[0028] the film thickness of the Ru film on the bottom of the hole beingnot less than 50% of the largest film thickness thereof in the hole.

[0029] Preferably, said hole has a depth of about 250 nm.

[0030] Preferably, an adhesive layer is formed between said Ru film andsaid silicon oxide film.

[0031] Preferably, said adhesive layer is made of tantalum oxide.

[0032] Preferably, the surface undulations of said Ru film are notgreater than 5 nm.

BRIEF DESCRIPTION OF THE DRAWINGS

[0033]FIG. 1 is a schematic cross sectional view of a principal part ofa semiconductor substrate, illustrating a step of the first embodimentof process for manufacturing a semiconductor integrated circuit deviceaccording to the invention;

[0034]FIG. 2 is a schematic plan view of a principal part of asemiconductor substrate, also illustrating the first embodiment ofprocess for manufacturing a semiconductor integrated circuit deviceaccording to the invention;

[0035]FIG. 3 is a schematic cross sectional view of a principal part ofa semiconductor substrate, illustrating another step of the firstembodiment of process for manufacturing a semiconductor integratedcircuit device according to the invention;

[0036]FIG. 4 is a schematic cross sectional view of a principal part ofa semiconductor substrate, illustrating still another step of the firstembodiment of process for manufacturing a semiconductor integratedcircuit device according to the invention;

[0037]FIG. 5 is a schematic cross sectional view of a principal part ofa semiconductor substrate, illustrating still another step of the firstembodiment of process for manufacturing a semiconductor integratedcircuit device according to the invention;

[0038]FIG. 6 is a schematic cross sectional view of a principal part ofa semiconductor substrate, illustrating still another step of the firstembodiment of process for manufacturing a semiconductor integratedcircuit device according to the invention;

[0039]FIG. 7 is a schematic cross sectional view of a principal part ofa semiconductor substrate, illustrating still another step of the firstembodiment of process for manufacturing a semiconductor integratedcircuit device according to the invention;

[0040]FIG. 8 is a schematic cross sectional view of a principal part ofa semiconductor substrate, illustrating still another step of the firstembodiment of process for manufacturing a semiconductor integratedcircuit device according to the invention;

[0041]FIG. 9 is a schematic cross sectional view of a principal part ofa semiconductor substrate, illustrating still another step of the firstembodiment of process for manufacturing a semiconductor integratedcircuit device according to the invention;

[0042]FIG. 10 is a schematic cross sectional view of a principal part ofa semiconductor substrate, illustrating still another step of the firstembodiment of process for manufacturing a semiconductor integratedcircuit device according to the invention;

[0043]FIG. 11 is a schematic cross sectional view of a principal part ofa semiconductor substrate, illustrating still another step of the firstembodiment of process for manufacturing a semiconductor integratedcircuit device according to the invention;

[0044]FIG. 12 is a schematic cross sectional view of a principal part ofa semiconductor substrate, illustrating still another step of the firstembodiment of process for manufacturing a semiconductor integratedcircuit device according to the invention;

[0045]FIG. 13 is a schematic cross sectional view of a principal part ofa semiconductor substrate, illustrating still another step of the firstembodiment of process for manufacturing a semiconductor integratedcircuit device according to the invention;

[0046]FIG. 14 is a schematic cross sectional view of a principal part ofa semiconductor substrate, illustrating still another step of the firstembodiment of process for manufacturing a semiconductor integratedcircuit device according to the invention;

[0047]FIG. 15 is a schematic cross sectional view of a principal part ofa semiconductor substrate, illustrating still another step of the firstembodiment of process for manufacturing a semiconductor integratedcircuit device according to the invention;

[0048]FIG. 16 is a schematic cross sectional view of a principal part ofa semiconductor substrate, illustrating still another step of the firstembodiment of process for manufacturing a semiconductor integratedcircuit device according to the invention;

[0049]FIG. 17 is a schematic cross sectional view of a principal part ofa semiconductor substrate, illustrating still another step of the firstembodiment of process for manufacturing a semiconductor integratedcircuit device according to the invention;

[0050]FIG. 18A is a graph showing the coating effect (b/a) of thepresent invention and

[0051]FIG. 18B is a schematic illustration of the coating effect (b/a)of the present invention;

[0052]FIG. 19 is a schematic plan view of a principal part of asemiconductor substrate, also illustrating the first embodiment ofprocess for manufacturing a semiconductor integrated circuit deviceaccording to the invention;

[0053]FIG. 20 is a schematic cross sectional view of a principal part ofa semiconductor substrate, illustrating a step of the second embodimentof process for manufacturing a semiconductor integrated circuit deviceaccording to the invention;

[0054]FIG. 21 is a schematic cross sectional view of a principal part ofa semiconductor substrate, illustrating another step of the secondembodiment of process for manufacturing a semiconductor integratedcircuit device according to the invention;

[0055]FIG. 22 is a schematic cross sectional view of a principal part ofa semiconductor substrate, illustrating still another step of the secondembodiment of process for manufacturing a semiconductor integratedcircuit device according to the invention;

[0056]FIG. 23 is a schematic cross sectional view of a principal part ofa semiconductor substrate, illustrating still another step of the secondembodiment of process for manufacturing a semiconductor integratedcircuit device according to the invention;

[0057]FIG. 24 is a schematic cross sectional view of a principal part ofa semiconductor substrate, illustrating still another step of the secondembodiment of process for manufacturing a semiconductor integratedcircuit device according to the invention;

[0058]FIG. 25A is a schematic cross sectional views of a principal partof a semiconductor substrate, illustrating a problem to be dissolved bythe present invention and FIG. 25B is also a schematic cross sectionalviews of a principal part of a semiconductor substrate, illustrating aproblem to be dissolved by the present invention; and

[0059]FIG. 26 is a schematic cross sectional view of a principal part ofa semiconductor substrate, illustrating another problem to be dissolvedby the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0060] Now, the present invention will be described by referring to theaccompanying drawings that illustrate preferred embodiments of theinvention. Throughout the drawings, components that are functionallysimilar to each other are denoted by a same reference symbol and willnot be described repeatedly.

[0061] (Embodiment 1)

[0062] This embodiment of process for manufacturing a DRAM will bedescribed on a step by step basis by referring to FIGS. 1 through 17.

[0063] For each element, firstly an isolation 2 is formed in the elementseparating region on the main surface of a semiconductor substrate(wafer) 1 that may typically be made of p-type single crystal silicon asshown in FIG. 1. Then, as shown in FIG. 2, oblong island-like activeregions (L) surrounded by the isolation 2 are produced simultaneouslywith the formation of the isolation 2. Thereafter, a pair of MISFET Qsfor memory cell selection that share either a source or a drain areformed in each of the active regions (L).

[0064] The isolation 2 is produced by etching the surface of thesemiconductor substrate 1 and forming about 300 to 400 nm deep groovesthere. Subsequently, a silicon oxide film 4 (about 600 nm thick) isformed on the semiconductor substrate 1 including inside of the grooveby deposition, using a CVD (Chemical Vapor Deposition) technique andthen the formed silicon oxide film 4 is polished back by ChemicalMechanical Polishing (CMP) technique.

[0065] Thereafter, a p-type well 3 is formed for each element in thesemiconductor substrate 1 by implanting boron (B). After cleansing thesurface of the p-type well 3 by means of a hydrofluoric acid typecleansing solution, an about 6 nm thick gate insulating film 5 is formedon the surface of the p-type well 3 (active region L) by thermallyoxidizing the semiconductor substrate 1.

[0066] Then, as shown in FIG. 3, a gate electrode 6 is formed for eachelement on the gate insulating film 5. More specifically, the gateelectrode 6 is produced by sequentially depositing an n-typepolycrystalline silicon film (about 70 nm thick) typically doped withphosphor (P), a barrier metal film (about 5 to 10 nm thick) of WN(tungsten nitride) or TiN (titanium nitride), a W film (about 100 nmthick) and a silicon nitride film 7 (about 150 nm thick) on the gateinsulating film 5 and dry-etching these films, using a photoresist filmas mask. The polycrystalline silicon film and the silicon nitride film 7are deposited by CVD, whereas the barrier metal film and the W film areformed by deposition, using a sputtering process. The gate electrode 6operates as a word line (WL). Thereafter, the gate electrode 6 issubjected to a wet hydrogen oxidation process to form a thin siliconoxide film on the wall side of n-type polycrystalline silicon fileconstituted as the gate electrode. The wet hydrogen oxidation processallows to selectively form an oxide film exclusive on silicon.

[0067] Then, as shown in FIG. 4, n-type semiconductor regions 8(source/drain) are formed respectively at the opposite sides of the gateelectrode 6 by implanting As (arsenal) or P (phosphor) in the p-typewell 3. The MISFET Qs for memory cell selection are substantiallycompleted by the above described steps.

[0068] Thereafter, a pair of contact holes 11, 12 are formed for eachelement on the n-type semiconductor regions 8 (source/drain) of theMISFET Qs for memory cell selection by depositing a silicon nitride film9 (about 50 nm thick) and a silicon oxide film 10 (about 600 nm thick)on the semiconductor substrate 1 by CVD, flattening the surface of thesilicon oxide film 10 by means of a chemical mechanical polishingtechnique and dry-etching the silicon oxide film 10 and the siliconnitride film 9, using a photoresist film (not shown) as mask. Theoperation of etching the silicon oxide film 10 is conducted with a largeselective ratio relative to the silicon nitride film, whereas that ofetching the silicon nitride film 9 is conducted with a large selectiveratio relative to silicon and the silicon oxide film. As a result, thecontact holes 11, 12 are formed to be self-aligned relative to the gateelectrode 6 (word line).

[0069] Then, as shown in FIG. 5, a plug 13 is formed in each of thecontact holes 11, 12 by depositing an n-type polycrystalline siliconfilm that is doped with P on the silicon oxide film 10 by means of CVDto bury the n-type polycrystalline silicon film in the contact holes 11,12 and subsequently removing the n-type polycrystalline silicon filmfrom the outside of the contact holes 11, 12 by chemical mechanicalpolishing (or by an etching back technique).

[0070] Then, after depositing a silicon oxide film 14 (about 150 nmthick) on the silicon oxide film 10 by CVD, a through hole 15 is formedby dry-etching the silicon oxide film 14 on the contact hole 11.

[0071] Then, a plug 16 is formed in the through hole 15 by depositing abarrier metal film that is a laminated film comprising a Ti film and TiNfilm formed on the silicon oxide film 14, subsequently depositing a Wfilm on the barrier metal film by CVD to bury the films in the throughhole 15 and then removing the films outside of the through hole 15 bychemical mechanical polishing. Thereafter, the n-type semiconductorregions (source/drain) of the MISFET Qs for memory cell selection andthe bit line BL which will be described hereinafter are connected by wayof the plugs 16 and 13.

[0072] Then, a bit line BL is formed on the silicon oxide film 14 andthe plug 16 by depositing a TiN film (about 10 nm thick, not shown) onthe silicon oxide film 14 by sputtering, subsequently depositing a Wfilm (about 50 nm thick) on the TiN film by CVD and dry-etching thesefilms, using a photoresist film (not shown) as mask.

[0073] Then, as shown in FIG. 6, a silicon oxide film 17 (about 300 nmthick) is formed on the bit line BL by CVD and then the surface of thefilm 17 is flattened by chemical mechanical polishing. Thereafter, athrough hole 19 is formed on each of the contact hole 12 containing theplug 13 buried therein by dry-etching the silicon oxide film 17.

[0074] The through hole 19 is made to show a diameter smaller than thatof the underlying contact hole 12. More specifically, the through hole19 is formed in a manner as described below. Firstly, a polycrystallinesilicon film 20 is deposited on the silicon nitride film 18 by CVD andthen a hole is formed by dry-etching the polycrystalline silicon film 20in the region for producing the through hole 19. Then, anotherpolycrystalline silicon film (not shown) is formed on thepolycrystalline silicon film 20. Subsequently, side wall spacers 21 areformed on the side walls of the hole by anisotropically etching thepolycrystalline silicon film on the polycrystalline silicon film 20 andthen the silicon nitride film 18 and the silicon oxide film 17 aredry-etched from the bottom of the hole by using the polycrystallinesilicon film 20 and the side wall spacers 21 as hard mask.

[0075] Then, the polycrystalline silicon film 20 and the side wallspacers 21 are removed by dry-etching and a plug 22 is formed in thethrough hole 19 as shown in FIG. 7. For forming the plug 22, an n-typepolycrystalline selection film is buried in the inside of the throughhole 19 by depositing an n-type polycrystalline silicon film that isdoped with P on the silicon nitride film 18 by CVD and subsequently then-type polycrystalline silicon film outside of the through hole 19 isremoved by chemical mechanical polishing (or by etching back).

[0076] Subsequently, an information storage capacity element C is formedon the plug 22. The element C comprises a lower electrode 30 comprisingRu films 30 a, 30 d, a capacitor insulating film made of a tantalumoxide film 32 and an upper electrode 33 made of W film/Ru film Theprocess of forming the information storage capacity element C will bedescribed in greater detail by referring to FIGS. 8 through 17. Thedrawings schematically illustrate the region for forming an informationstorage capacity element C located on the plug 22.

[0077] Firstly, referring to FIG. 8, a silicon nitride film 18 isdeposited on the plug 22 and the silicon oxide film 17 with a filmthickness of about 50 nm by CVD and subsequently a silicon oxide film 24is deposited on the silicon nitride film 18. The lower electrode of theinformation storage capacity element C is formed in the hole (recess) ofthe silicon oxide film 24 that is produced in the next step. The siliconoxide film 24 needs to be deposited to show a large thickness (about 0.8μm) in order to make the lower electrode have a large surface area andshow a large stored charge. The silicon oxide film 24 is typicallydeposited by plasma CVD, using a mixture of oxygen and tetraethoxysilane(TEOS) as source gas and subsequently the surface thereof is flattenedby chemical mechanical polishing, if necessary.

[0078] Then, a hard mask 26 that is made of a tungsten film is formed onthe silicon oxide film 24. The hard mask 26 may be made of metal otherthan tungsten.

[0079] Thereafter, as shown in FIG. 9, a photoresist film (not shown) isformed on the hard mask 26 and the hard mask 26 is dry-etched by usingthe photoresist film as mask. Subsequently, a deep hole (recess) 27 isformed by dry-etching the silicon oxide film 24 and the silicon nitridefilm 18, using the hard mask 26 as a mask. The surface of the plug 22 inthe through hole 19 is exposed through the bottom of the deep hole(recess) 27.

[0080] Then, the hard mask 26 remaining on the silicon oxide film 24 isremoved by means of a solution containing hydrogen peroxide and antantalum oxide film 29 (about 10 nm thick) is deposited on the siliconoxide film 24 and in the hole 27 by CVD as shown in FIG. 10. Such atantalum oxide film can be formed by using Ta(OC₂H₅)₅ and O₂ as sourcegas at temperature between 400 and 450° C. The tantalum oxide film 29 ishighly adhesive relative to the underlying silicon oxide film 24 andalso to the Ru films 30 (30 a, 30 d) which will be described hereinafterso that it is used to operate as adhesive layer. A tantalum nitride filmmay alternatively be used as adhesive layer.

[0081] Thereafter, as shown in FIG. 11, the tantalum oxide film 29 onthe silicon oxide film 24 and the bottom of the hole 27 is removed byanisotropically etching it. Thus, the tantalum oxide film 29 is leftonly on the side wall of the hole 27. If a tantalum nitride film is usedas adhesive layer, the tantalum nitride film on the bottom of the hole27 does not need to be removed because it is electrically conductive.

[0082] Then, as shown in FIG. 12, an Ru film 30 (about 5 nm thick) isdeposited on the silicon oxide film 24 and in the hole 27 by CVD. Notethat the Ru film can be formed efficiently by CVD when a thin Ru film isformed by sputtering before depositing the Ru film by CVD because thefilm formed by sputtering operates as seed.

[0083] Now, the requirements that need to be met when forming the Rufilm 30 a will be discussed below. The Ru film 30 a is typically formedby CVD, introducing a tetrahydrofuran solution ofethylcyclopentadieneruthenium (Ru(C₂H₅C₅H₄)₂), O₂ and N₂ at respectiverates of 5 cm³/min, 50cm³/min (the volume as used herein is expressed interms of the value under standard conditions (at 0° C. under 1atmospheric pressure(1.01325×10⁵ Pa)) and expressed by using “sccm”hereinafter) and 900 “sccm” at 290° C. under the pressure of 665 Pa.When the film is formed under these conditions, the ratio (b/a (%)) ofthe smallest film thickness “b” that is found on the bottom of the deepgroove to the largest film thickness “a” of the Ru film formed on theside wall and the bottom of the hole, can be held to not less than 50%.

[0084]FIG. 18A is a graph showing the relationship between the coatingeffect and the ratio of the flow rates of the raw materials(Ru(C₂H₅C₅H₄)₂ /O₂) that can be observed when forming an Ru film in adeep hole by CVD. The expression of coating effect as used herein refersto the ratio of the smallest film thickness “b” that is found on thebottom of the deep groove to the largest film thickness “a” (b/a (%) ofthe Ru film formed on the side wall and the bottom of the hole. Theratio of the flow rates of the raw materials (Ru(C₂H₅C₅H₄)₂ /O₂) as usedherein refers to the ratio of the volume of the gaseous raw material ofRu(C₂H₅C₅H₄)₂ that is originally liquid and gasified in a gasifier tothe volume of O₂ (gas flow rate ratio). The deep hole has a diameter of250 nm and a depth of 1,500 nm (depth/diameter=6). The O₂ flow rate ismade equal to 50 sccm.

[0085] As seen from FIG. 18A, the coating effect is very poor and no Rufilm is formed on the bottom of the deep hole when the flow rate ratiois less than 5%. An Ru film starts forming on the deep hole bottom whenthe flow rate ratio exceeds 5%. The coating effect remarkably improvesto go over 50% when the flow rate ratio exceeds 10%. Finally, thecoating effect becomes practically equal to 100% when the flow rateratio exceeds 20%.

[0086] Therefore, when an Ru film is formed by introducing atetrahydrofuran solution (0.1 mol/lit.) of ethylcyclopentadieneruthenium(Ru(C₂H₅C₅H₄)₂), O₂ and N₂ at respective rates of 5cm³/min, 50 sccm and900 sccm, the ethylcyclopentadieneruthenium solution is supplied at arate of 0.0005 mol/min, which is equal to a gas supply rate of about 11cm³/min as calculated by means of the equation of state of gas or PV=nRT(P: pressure (atm), V: volume (lit.), n: number of mols (mol), R: gasconstant (0.082), T: absolute temperature (K)) when the conditions arereduced to 1 atmospheric pressure (1.01325×105 Pa) and 273K. Thus, theflow rate ratio is about 22%, signifying a coating effect of about 100%.

[0087] While the flow rate of O₂ is 50 sccm in FIG. 18, the flow rate ofthe supplied oxygen gas is not limited thereto and oxygen gas may wellbe supplied at rate that is sufficient for decomposing the organicgroups of Ru(C₂H₅C₅H₄)₂. More specifically, under the above listedconditions, the organic groups of Ru(C₂H₅C₅H₄)₂ can be decomposed whenoxygen gas is supplied at a rate of about 10 sccm. While the filmforming temperature is 290° C. in the above description, any appropriatetemperature may be selected below 300° C.

[0088] As a flow rate ratio of Ru(C₂H₅C₅H₄)₂ /O₂ not less than 10% isselected for this embodiment, the film thickness of the Ru film on thebottom of the deep hole is not less than 50% of the largest filmthickness “a” of the Ru film.

[0089] Then, as shown in FIG. 13, the work is subjected to a heattreatment process at 600° C. for one minute in a non-oxidizingatmosphere. As a result of this heat treatment, a silicide reactionoccurs in the contact area of the plug 22 and the Ru film 30 to produceruthenium silicide 30 b on the bottom of the hole 27. However, nosilicidizing reaction takes place on the side wall and at the outside ofthe hole 27 and hence no ruthenium silicide is produced because nounderlying silicon exists there. Thus, ruthenium silicide 30 b can beformed in a self-aligning manner on the bottom surface of the hole 27.

[0090] Thereafter, the work is subjected to another heat treatmentprocess at 700° C. for one minutes in an ammonia (NH₃) atmosphere toform ruthenium silicon nitride (RuSiN) 30 c on the surface of theruthenium silicide 30 b. The RuSiN formed under the above conditionsshows a film thickness of about 1 nm. The film thickness of the RuSiNfilm 30 c can be produced by controlling the heat treatment temperature.The Ru film 30 d to be formed thereon and the plug 22 will not beelectrically connect to each other satisfactorily when the thickness ofthe RuSiN film is too large, whereas the Ru film 30 d and the plug 22will not be prevented from being silicidized when the thickness of theRuSiN film is too small. Therefore, it is desirable to make thethickness of the RuSiN film between 0.5 and 1.0 nm in order to securethe electric connection of the Ru film 30 d and the plug 22 and suppressthe silicidizing reaction.

[0091] Then, as shown in FIG. 14, an about 20 nm thick Ru film 30 d isformed on the Ru film 30 a and the RuSiN film 30 c by CVD, introducing atetrahydrofuran solution of ethylcyclopentadieneruthenium(Ru(C₂H₅C₅H₄)₂)₂/O₂ and N₂ at respective rates of 5 cm³/min, 50 sccm and900 sccm at 290° C. under the pressure of 665 Pa.

[0092] As a flow rate ratio of Ru(C₂H₅C₅H₄)₂/O₂ not less than 10% isselected for forming the Ru film 30 d, the film thickness of the Ru filmon the bottom of the deep hole can be secured to be not less than 50% ofthe largest film thickness of the Ru film.

[0093] As a flow rate ratio of Ru(C₂H₅C₅H₄)₂/O₂ not less than 10% isselected for forming the Ru film 30 d, the film thickness of the Ru filmon the bottom of the deep hole is not less than 50% of the largest filmthickness of the Ru film as in the case of forming the Ru film 30 a.Thus, it is possible to uniformly produce the Ru films 30 a, 30 d in adeep hole. As a result, the undulations of the Ru films can be reduced(to less than 5 nm).

[0094] Thereafter, photoresist (not shown) is applied onto the Ru film30 d. Then, the entire surface is exposed to light and developed so thatthe photoresist film (not shown) is left only in the hole 27. Thephotoresist film operates as protection film for preventing the Ru films30 a, 30 d from being removed from the inside (the side all and thebottom) of the hole 27 when the unnecessary parts of the Ru films 30 a,30 d are removed from the top of the silicon oxide film 24 by dryetching in the next step. Then, a lower electrode 30 is produced byremoving the Ru films 30 a, 30 d on the silicon oxide film 24 by dryetching, using the photoresist film as mask. Subsequently, thephotoresist film in the hole 27 is removed (FIG. 15).

[0095] Then, as shown in FIG. 16, a tantalum oxide film 32 is depositedin the inside of the hole 27 where the lower electrode 30 is formed andon the silicon oxide film 24 and used as capacity insulating film by CVDto a thickness of about 15 nm.

[0096] Thereafter, the tantalum oxide film 32 is heat-treated at about700° C. for two minutes in a nitrogen atmosphere to crystallize thetantalum oxide and then at about 550° C. for one minutes in an oxygenatmosphere to improve the film quality of the tantalum oxide film.

[0097] Then, as shown in FIG. 17, an upper electrode 33 is formed on thetantalum oxide film 32 by depositing an Ru film 33 a (about 70 nm thick)and a W film 33 b (about 100 nm thick) by CVD on the tantalum oxide film32. The W film is used to reduce the contact resistance between theupper electrode 33 and the upper wiring. Additionally, a TiN film may beformed between the Ru film and the W film in order to prevent anyincrease of resistance due to diffusion of gas (oxygen and/or hydrogen)from the capacity insulating film (tantalum oxide film 32) into the Wfilm.

[0098] Thus a complete information storage capacity element C comprisinga lower electrode 30 formed by the Ru films 30 a, 30 d, a capacityinsulating film formed by the tantalum oxide film 32 and an upperelectrode 33 formed by a W film 33 b and an Ru film 33 b is produced asa result of the above described steps so that the process of formingmemory cells of a DRAM comprising MISFET Qs for memory cell selectionand information storage capacity elements C connected to them in seriesis substantially completed. FIG. 19 is a schematic plan view of asemiconductor integrated circuit device after forming informationstorage capacity elements C. It will be appreciated that FIG. 7 is across sectional view taken along line A-A in FIG. 19.

[0099] Thereafter, an interlayer insulating film 34 which may typicallybe a silicon oxide film is formed on the information storage capacityelements C.

[0100] Then, although not shown, Al wires are arranged normally in twolayers on the interlayer insulating film and a passivation film isformed on the top Al wiring layer.

[0101] As described above in detail, with this embodiment, it ispossible to etch Ru films at an enhanced rate with a large selectiveratio relative to resist. Therefore, it is possible to form lowerelectrodes of information storage capacity elements in respective holesshowing a high aspect ratio at a high yield.

[0102] (Embodiment 2)

[0103] While the ruthenium silicon nitride (RuSiN) 30 c is formed asbarrier layer on the plug 22 after forming a deep hole 27 in the abovedescribed first embodiment, a barrier layer typically made of tantalumnitride or titanium nitride may be formed before forming the deep hole27.

[0104]FIG. 20 is a schematic illustration of an area where aninformation storage capacity element C is to be formed on a plug 22. Thesteps down to the formation of the plug 22 of this embodiment are sameas those of the first embodiment described above by referring to FIGS. 1through 7 and hence will not be described here any further.

[0105] With the second embodiment, a barrier metal film 23 is formed onthe plug 22. More specifically, the barrier metal film 23 is formedfirstly by making the surface of the plug 22 retreat to a level lowerthan the surface of the silicon nitride film 18 by etching to secure aspace for burying the barrier metal film 23 on the plug 22. Then, a TiNfilm is buried in the above space on the plug 22 by depositing the TiNfilm on the silicon oxide film 17 by sputtering and subsequently the TiNfilm is removed from the outside of the space by chemical mechanicalpolishing (or etching back). Note that the space may alternatively besecured by overpolishing (over-etching) the n-type polycrystallinesilicon film inside the through hole 19 at the time of forming the plug22, where the n-type polycrystalline silicon film is buried in theinside of the through hole 19 by deposing the film that is doped with Pon the silicon oxide film 17 and subsequently the n-type polycrystallinesilicon film is removed from the outside of the through hole 19 bychemical mechanical polishing (or etching back).

[0106] Then, as shown in FIG. 21, an about 50 nm thick silicon nitridefilm 18 is deposited on the plug 22 and the silicon oxide film 17 by CVDand subsequently a silicon oxide film 24 is deposited on the siliconnitride film 18. The lower electrode of the information storage capacityelement C is formed in the inside of the hole (recess) that is formed inthe silicon oxide film 24 in the next step. For the electrode to show alarge surface area in order to increase the stored charge, it isnecessary to make the silicon oxide film 24 have a large film thickness(about 0.8 μm). The silicon oxide film 24 can be formed by means of aplasma CVD process, using oxygen and tetraethoxysilane (TEOS) as sourcegas. If necessary, subsequently the surface is flattened by chemicalmechanical polishing.

[0107] Thereafter, a hard mask 26 made of a tungsten film is formed onthe silicon oxide film 24, although the hard mask 26 may alternativelybe made of metal other than tungsten.

[0108] Subsequently, a phororesist film (not shown) is formed on thehard mask 26, which is then subjected to a dry etching operation, usingthe photoresist film as mask. Thereafter, both the silicon oxide film 24and the silicon nitride film 18 are subjected to a dry etchingoperation, using the hard mask 26, to produce a deep hole (recess) 27.The surface of the barrier metal film 23 on the plug 22 is exposedthrough the bottom of the deep hole (recess) 27.

[0109] Then, after removing the hard mask 26 remaining on the siliconoxide film 24 by means of a solution containing hydrogen peroxide, atantalum oxide film 29 (about 10 nm thick) is deposed on the siliconoxide film 24 and in the inside of the hole 27 by CVD, using Ta(OC₂H₅)₅and O₂ as source gas at temperature between 400 and 450° C. The tantalumoxide film 29 is highly adhesive relative to the underlying siliconoxide film 24 and also to the Ru films 30 which will be describedhereinafter so that it is used to operate as adhesive layer. A tantalumnitride film may alternatively be used as adhesive layer.

[0110] Thereafter, as shown in FIG. 23, the tantalum oxide film 29 onthe silicon oxide film 24 and the bottom of the hole 27 is removed byanisotropically etching it. Thus, the tantalum oxide film 29 is leftonly on the side wall of the hole 27. If a tantalum nitride film is usedas adhesive layer, the tantalum nitride film on the bottom of the hole27 does not need to be removed because it is electrically conductive.

[0111] Then, as shown in FIG. 24, an Ru film 30 a (about 20 nm thick) isdeposited on the silicon oxide film 24 and in the hole 27 by CVD. Notethat the Ru film can be formed efficiently by CVD when a thin Ru film isformed by sputtering before depositing the Ru film by CVD because thefilm formed by sputtering operates as seed.

[0112] Now, the requirements that need to be met when forming the Rufilm 30 a will be discussed below. The Ru film 30 a is typically formedby CVD, introducing a tetrahydrofuran solution ofethylcyclopentadieneruthenium (Ru(C₂H₅C₅H₄)₂), O₂ and N₂ at respectiverates of 5 cm³/min, 50 sccm and 900 sccm at 290° C. under the pressureof 665 Pa. When the film is formed under these conditions, the ratio(b/a) of the smallest film thickness “b” of the Ru film that is formedon the bottom of the hole 27 to the largest film thickness “a” of the Rufilm formed on the side wall of the hole 27 can be held to not less than50% as described earlier by referring to FIG. 18.

[0113] All the subsequent steps are same as their counterparts ofEmbodiment 1 described earlier by referring to FIGS. 16 and 17 and hencewill not be described here any further.

[0114] The present invention is described in detail above specificallyby referring to the preferred embodiments. However, the presentinvention is by no means limited to the described embodiments, which maybe modified and/or altered in various different ways without departingfrom the scope of the present invention.

[0115] Some of the typical advantages of the present invention will besummarized below.

[0116] According to the invention, the conditions for forming Ru filmscan be optimized to produce excellent Ru films. For example, the ratioof the smallest film thickness that is found on the bottom of the deepgroove to the largest film thickness “a” of the Ru film formed on theside wall and the bottom of the hole can be held to not less than 50%when the flow rate ratio is made greater than 10%.

[0117] As a result, the lower electrode of each information storagecapacity element can be accurately formed in a deep hole to improve theperformance of the element. Then, the yield of manufacturingsemiconductor integrated circuit devices such as DRAMs can be improved.

What is claimed is:
 1. A process for manufacturing a semiconductor integrated circuit device comprising: (a) a step of forming a MISFET for memory cell selection on a main surface of a semiconductor substrate; (b) a step of forming a plug electrically connected to a source/drain region of said MISFET for memory cell selection; (c) a step of forming a silicon oxide film over said plug; (d) a step of forming a hole getting to a surface of said plug in said silicon oxide film; (e) a step of forming an Ru film over a side wall and a bottom of said hole by causing an organic compound of Ru and an oxidizing agent, a gasification flow rate of the organic compound of Ru being not less than 5% of a flow rate of the oxidizing agent; (f) a step of forming a capacity insulating film over said Ru film; and (g) a step of forming an upper electrode on said capacity insulating film.
 2. The method according to claim 1, wherein reaction of said organic compound of Ru and said oxidizing agent is conducted at temperature not higher than 300° C.
 3. A semiconductor integrated circuit device comprising: (a) a MISFET for memory cell selection formed on a main surface of a semiconductor substrate; (b) a plug electrically connected to a source/drain region of said MISFET for memory cell selection; (c) a silicon oxide film formed over said plug; (d) a hole formed in said silicon oxide film and extending to a surface of said plug; said hole having a depth not less than five times of short diameter thereof; (e) an Ru film formed in said hole, a capacity insulating film formed over the Ru film and an upper electrode formed on said capacity insulating film; film thickness of the Ru film over a bottom of the hole being not less than 50% of the largest film thickness thereof in the hole.
 4. The device according to claim 3, wherein an adhesive layer is formed between said Ru film and said silicon oxide film.
 5. The device according to claim 3, wherein surface undulations of said Ru film are not greater than 5 nm.
 6. A process for manufacturing a semiconductor integrated circuit device comprising: (a) a step of forming an interlayer insulating film over a semiconductor substrate; (b) a step of forming a hole in said interlayer insulating film; (c) a step of forming a first electrically conductive film over a side wall and a bottom of said hole by causing an organic compound of said first electrically conductive film and an oxidizing agent, a gasification flow rate of said organic compound of said first electrically conductive film being not less than 5% of a flow rate of the oxidizing agent; (d) a step of forming an insulating film over said first electrically conductive film; and (e) a step of forming a second electrically conductive film on said insulating film.
 7. The method according to claim 6, wherein depth of said hole is not less than five times of short diameter of said hole.
 8. The method according to claim 6, wherein ratio of film thickness of the first electrically conductive film over the bottom of the hole to the largest film thickness of said first electrically conductive film in the hole is not less than 50%.
 9. The method according to claim 6, wherein said first electrically conductive film is made of Ru.
 10. The method according to claim 6, wherein reaction of the organic compound of said first electrically conductive film and the oxidizing agent is conducted at temperature not higher than 300° C. 